SMMU_ITOP_GLBL (SMMU500) Register Description
| Register Name | SMMU_ITOP_GLBL |
|---|---|
| Offset Address | 0x0000002008 |
| Absolute Address | 0x00FD802008 (SMMU_GPV) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | For integration test purposes, allows to enable or disable secure and nonsecure interrupts and write or read most significant bits of TCU MTLB and IPA RAMS. |
SMMU_ITOP_GLBL (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TCU_RAM_DATA | 19:16 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| GLBLSF1 | 9 | roRead-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| GLBLNSF1 | 1 | roRead-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |