GSTS (USB3_XHCI) Register Description
Register Name | GSTS |
---|---|
Offset Address | 0x000000C118 |
Absolute Address |
0x00FE20C118 (USB3_0_XHCI) 0x00FE30C118 (USB3_1_XHCI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Global Status Register |
GSTS (USB3_XHCI) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
CBELT | 31:20 | roRead-only | 0 | Current BELT Value In Host mode, this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command. |
Reserved | 19:12 | roRead-only | 0x0 | Reserved |
SSIC_IP | 11 | roRead-only | 0 | SSIC interrupt pending (SSIC_IP) This field indicates that there is a pending interrupt related to SSIC in the SEVT register. |
OTG_IP | 10 | roRead-only | 0 | OTG Interrupt Pending This field indicates that there is a pending interrupt pertaining to OTG in OEVT register. |
BC_IP | 9 | roRead-only | 0 | Battery Charger Interrupt Pending This field indicates that there is a pending interrupt pertaining to BC in BCEVT register. |
ADP_IP | 8 | roRead-only | 0 | ADP Interrupt Pending This field indicates that there is a pending interrupt pertaining to ADP in ADPEVT register. |
Host_IP | 7 | roRead-only | 0 | Host Interrupt Pending: This field indicates that there is a pending interrupt pertaining to xHC in the Host event queue. |
Device_IP | 6 | roRead-only | 0 | Device Interrupt Pending This field indicates that there is a pending interrupt pertaining to peripheral (device) operation in the Device event queue. |
CSRTimeout | 5 | wtcReadable, write a 1 to clear | 0x0 | CSR Timeout When this bit is 1b1, it indicates that the software performed a write or read to a core register that could not be completed within `DWC_USB3_CSR_ACCESS_TIMEOUT bus clock cycles (default: h1FFFF). |
BUSERRADDRVLD | 4 | wtcReadable, write a 1 to clear | 0x0 | Bus Error Address Valid (BusErrAddrVld) Indicates that the GBUSERRADDR register is valid and reports the first bus address that encounters a bus error. Note: Only supported in AHB and AXI configurations. |
Reserved | 3:2 | roRead-only | 0x0 | Reserved |
CURMOD | 1:0 | roRead-only | 0 | Current Mode of Operation (CurMod) Indicates the current mode of operation: - 2b00: Device mode - 2b01: Host mode |