GSTS (USB3_XHCI) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GSTS (USB3_XHCI) Register Description

Register NameGSTS
Offset Address0x000000C118
Absolute Address 0x00FE20C118 (USB3_0_XHCI)
0x00FE30C118 (USB3_1_XHCI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionGlobal Status Register

GSTS (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CBELT31:20roRead-only0Current BELT Value
In Host mode, this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command.
Reserved19:12roRead-only0x0Reserved
SSIC_IP11roRead-only0SSIC interrupt pending (SSIC_IP)
This field indicates that there is a pending interrupt related to SSIC in the SEVT register.
OTG_IP10roRead-only0OTG Interrupt Pending
This field indicates that there is a pending interrupt pertaining to OTG in OEVT register.
BC_IP 9roRead-only0Battery Charger Interrupt Pending
This field indicates that there is a pending interrupt pertaining to BC in BCEVT register.
ADP_IP 8roRead-only0ADP Interrupt Pending
This field indicates that there is a pending interrupt pertaining to ADP in ADPEVT register.
Host_IP 7roRead-only0Host Interrupt Pending:
This field indicates that there is a pending interrupt pertaining to xHC in the Host event queue.
Device_IP 6roRead-only0Device Interrupt Pending
This field indicates that there is a pending interrupt pertaining to peripheral (device) operation in the Device event queue.
CSRTimeout 5wtcReadable, write a 1 to clear0x0CSR Timeout
When this bit is 1b1, it indicates that the software performed a write or read to a core register that could not be completed within `DWC_USB3_CSR_ACCESS_TIMEOUT bus clock cycles (default: h1FFFF).
BUSERRADDRVLD 4wtcReadable, write a 1 to clear0x0Bus Error Address Valid (BusErrAddrVld)
Indicates that the GBUSERRADDR register is valid and reports the first bus address that encounters a bus error.
Note: Only supported in AHB and AXI configurations.
Reserved 3:2roRead-only0x0Reserved
CURMOD 1:0roRead-only0Current Mode of Operation (CurMod)
Indicates the current mode of operation:
- 2b00: Device mode
- 2b01: Host mode