EVCNTR1_EL0 (A53_PMU_3) Register Description
| Register Name | EVCNTR1_EL0 |
|---|---|
| Offset Address | 0x0000000008 |
| Absolute Address | 0x00FEF30008 (CORESIGHT_A53_PMU_3) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Performance Monitors Event Count Registers |
EVCNTR1_EL0 (A53_PMU_3) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| EVCNTR1_EL0 | 31:0 | rwNormal read/write | 0x0 | Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30. |