DATA_0_RO (GPIO) Register Description
| Register Name | DATA_0_RO |
|---|
| Offset Address | 0x0000000060 |
|---|
| Absolute Address |
0x00FF0A0060 (GPIO)
|
|---|
| Width | 32 |
|---|
| Type | mixedMixed types. See bit-field details. |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | Input Data (GPIO Bank0, MIO) |
|---|
This register enables software to observe the value on the device pin. If the GPIO signal is configured as an output, then this would normally reflect the value being driven on the output. Writes to this register are ignored. This register reflects the input values for bank0, which corresponds to MIO[25:0]. NOTE: If the MIO is not configured to enable this pin as a GPIO pin, then DATA_RO is unpredictable. In other words, software cannot observe values on non-GPIO pins through the GPIO registers.
DATA_0_RO (GPIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:26 | razRead as zero | 0x0 | Not used, read back as zero |
| DATA_0_RO | 25:0 | roRead-only | 0 | Input Data |