SD_OTAPDLYSEL (IOU_SLCR) Register Description
| Register Name | SD_OTAPDLYSEL |
|---|---|
| Offset Address | 0x0000000318 |
| Absolute Address | 0x00FF180318 (IOU_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Output Tap Delay Select |
SD_OTAPDLYSEL (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:23 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
| SD1_OTAPDLYENA | 22 | rwNormal read/write | 0x0 | Reserved. Leave this bit set to 0. |
| SD1_OTAPDLYSEL | 21:16 | rwNormal read/write | 0x0 | Selects optimal number of taps on the SD_CLK. This is effective only when corectrl_otapdlyena is asserted. For the SD frequency od - 200 MHz: 8 taps are available 100 MHz: 15 taps are available 50 MHz: 30 taps are available 33 MHz: 45 taps are available |
| Reserved | 15:7 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
| SD0_OTAPDLYENA | 6 | rwNormal read/write | 0x0 | Reserved. Leave this bit set to 0. |
| SD0_OTAPDLYSEL | 5:0 | rwNormal read/write | 0x0 | Selects optimal number of taps on the SD_CLK. This is effective only when [SD_OTAPDLYENA] is asserted. For the SD frequency od - 200 MHz: 8 taps are available 100 MHz: 15 taps are available 50 MHz: 30 taps are available 33 MHz: 45 taps are available |