SD_CONFIG_REG3 (IOU_SLCR) Register Description
| Register Name | SD_CONFIG_REG3 |
|---|---|
| Offset Address | 0x0000000324 |
| Absolute Address | 0x00FF180324 (IOU_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x06070607 |
| Description | SD Configuration, Reg 3. |
SD_CONFIG_REG3 (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:27 | razRead as zero | 0x0 | reserved. |
| SD1_TUNINGSDR50 | 26 | rwNormal read/write | 0x1 | Use Tuning for SDR50 This bit should be set if the Application wants Tuning be used for SDR50 Modes. The Core operates with or with out tuning for SDR50 mode as long as the Clock can be manually tuned using tap delay. |
| SD1_RETUNETMR | 25:22 | rwNormal read/write | 0x8 | This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved |
| SD1_DDRIVER | 21 | rwNormal read/write | 0x0 | reserved; Driver Type D not supported. |
| SD1_CDRIVER | 20 | rwNormal read/write | 0x0 | reserved; Driver Type C not supported. |
| SD1_ADRIVER | 19 | rwNormal read/write | 0x0 | reserved; Driver Type A not supported. |
| SD1_DDR50 | 18 | rwNormal read/write | 0x1 | DDR50 mode Support 1: DDR50 supported 0: DDR50 not supported |
| SD1_SDR104 | 17 | rwNormal read/write | 0x1 | SDR104 mode Support 1: SDR104 supported 0: SDR104 not supported |
| SD1_SDR50 | 16 | rwNormal read/write | 0x1 | SDR50 mode Support 1: SDR50 supported 0: SDR50 not supported |
| Reserved | 15:11 | razRead as zero | 0x0 | reserved |
| SD0_TUNINGSDR50 | 10 | rwNormal read/write | 0x1 | Use Tuning for SDR50 This bit should be set if the Application wants Tuning be used for SDR50 Modes. The Core operates with or with out tuning for SDR50 mode as long as the Clock can be manually tuned using tap delay. |
| SD0_RETUNETMR | 9:6 | rwNormal read/write | 0x8 | This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved |
| SD0_DDRIVER | 5 | rwNormal read/write | 0x0 | Driver Type D Support This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not. |
| SD0_CDRIVER | 4 | rwNormal read/write | 0x0 | Driver Type C Support This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not. |
| SD0_ADRIVER | 3 | rwNormal read/write | 0x0 | Driver Type A Support This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not. |
| SD0_DDR50 | 2 | rwNormal read/write | 0x1 | DDR50 mode Support 1: DDR50 supported 0: DDR50 not supported |
| SD0_SDR104 | 1 | rwNormal read/write | 0x1 | SDR104 mode Support 1: SDR104 supported 0: SDR104 not supported |
| SD0_SDR50 | 0 | rwNormal read/write | 0x1 | SDR50 mode Support 1: SDR50 supported 0: SDR50 not supported |