L2_PLL_SS_STEP_SIZE_3_MSB (SERDES) Register Description
| Register Name | L2_PLL_SS_STEP_SIZE_3_MSB |
|---|---|
| Offset Address | 0x000000A37C |
| Absolute Address | 0x00FD40A37C (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L2_PLL_SS_STEP_SIZE_3_MSB (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PLL_SS_STEP_SIZE_3_MSB_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| tm_force_en_ss | 7 | rwNormal read/write | 0x0 | Value generated by PCW. |
| tm_en_ss | 6 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_ss_num_of_steps | 5 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_ss_step_size | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| ss_spread_type | 3:2 | rwNormal read/write | 0x0 | Value generated by PCW. |
| ss_step_size_3_msb | 1:0 | rwNormal read/write | 0x0 | Value generated by PCW. |