SMMU_CB1_PMEVCNTR0 (SMMU500) Register Description
| Register Name | SMMU_CB1_PMEVCNTR0 |
|---|---|
| Offset Address | 0x0000011E00 |
| Absolute Address | 0x00FD811E00 (SMMU_GPV) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter. |
SMMU_CB1_PMEVCNTR0 (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| bits | 31:0 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |