Field Name | Bits | Type | Reset Value | Description |
NSCFG | 29:28 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
WACFG | 27:26 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
RACFG | 25:24 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
SHCFG | 23:22 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
FB | 21 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
MTCFG | 20 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
MemAttr | 19:16 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TRANSIENTCFG | 15:14 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
PTW | 13 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
ASIDPNE | 12 | roRead-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
UWXN | 10 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
WXN | 9 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
HUPCF | 8 | rwNormal read/write | 0x1 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
CFCFG | 7 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
CFIE | 6 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
CFRE | 5 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
E | 4 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
AFFD | 3 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
AFE | 2 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TRE | 1 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
M | 0 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |