SMMU_CB14_TTBR0_low (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_CB14_TTBR0_low (SMMU500) Register Description

Register NameSMMU_CB14_TTBR0_low
Offset Address0x000001E020
Absolute Address 0x00FD81E020 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionThe Translation Table Base register 0 holds the base address of the translation table 0.

SMMU_CB14_TTBR0_low (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ADDRESS_31_731:7rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ADDRESS_6_IRGN0 6rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ADDRESS_5_NOS 5rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ADDRESS_4_3_RGN 4:3rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ADDRESS_2 2roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ADDRESS_1_S 1rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ADDRESS_0_IRGN1 0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details