IDR_0 (SMMU_REG) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

IDR_0 (SMMU_REG) Register Description

Register Name	IDR_0
Offset Address	0x000000001C
Absolute Address	0x00FD5F001C (SMMU_REG)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000000
Description	Interrupt Disable Register. A write of 1 to this location will mask the interrupt

IDR_0 (SMMU_REG) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
addr_decode_err	31	wtcReadable, write a 1 to clear	0x0	Address Decode Error
Reserved	30:5	roRead-only	0x0	Reserved
gbl_flt_irpt_ns	4	woWrite-only	0x0	Interrupt Disable for gbl_flt_irpt_ns interrupt.
gbl_flt_irpt_s	3	woWrite-only	0x0	Interrupt Disable for gbl_flt_irpt_s interrupt.
comb_perf_irpt_TBU	2	woWrite-only	0x0	Interrupt Disable for comb_perf_irpt_TBU interrupt.
comb_irpt_s	1	woWrite-only	0x0	Interrupt Disable for comb_irpt_s interrupt.
comb_irpt_ns	0	woWrite-only	0x0	Interrupt Disable for comb_irpt_ns interrupt.