INT_MASK_4 (GPIO) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

INT_MASK_4 (GPIO) Register Description

Register NameINT_MASK_4
Offset Address0x000000030C
Absolute Address 0x00FF0A030C (GPIO)
Width32
TyperoRead-only
Reset Value0xFFFFFFFF
DescriptionInterrupt Mask Status (GPIO Bank4, EMIO Bank1)

This register operates in exactly the same manner as INT_MASK_0, except that it reflects bank4, which corresponds to EMIO[63:32].

INT_MASK_4 (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
INT_MASK_431:0roRead-only0xFFFFFFFFInterrupt mask
0: interrupt source enabled
1: interrupt source masked
Each bit reports the status for the corresponding pin within the 32-bit bank