ATTR_52 (PCIE_ATTRIB) Register Description
| Register Name | ATTR_52 |
|---|---|
| Offset Address | 0x00000000D0 |
| Absolute Address | 0x00FD4800D0 (PCIE_ATTRIB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000040 |
| Description | ATTR_52 |
This register should only be written to during reset of the PCIe block
ATTR_52 (PCIE_ATTRIB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr_pm_cap_id | 13:6 | rwNormal read/write | 0x1 | The capability identifier of power management capability. The value is transferred to the PM Capabilities Register[7:0]. |
| attr_pm_cap_dsi | 5 | rwNormal read/write | 0x0 | Device Specific Initialization (DSI). Transferred to the PM Capabilities register[21]. |
| attr_pm_cap_d2support | 4 | rwNormal read/write | 0x0 | D2 Support. Transferred to the PM Capabilities register[26]. |
| attr_pm_cap_d1support | 3 | rwNormal read/write | 0x0 | D1 Support. Transferred to the PM Capabilities register[25]. |
| attr_pm_cap_auxcurrent | 2:0 | rwNormal read/write | 0x0 | AUX Current. Requested aux current allocation. Transferred to the PM Capabilities register[24:22]. |