PxCMD (SATA_AHCI_PORTCNTRL) Register Description
| Register Name | PxCMD |
|---|---|
| Offset Address | 0x0000000018 |
| Absolute Address |
0x00FD0C0118 (SATA_AHCI_PORT0_CNTRL) 0x00FD0C0198 (SATA_AHCI_PORT1_CNTRL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00400000 |
| Description | Port x Command and Status (PxCMD) |
PxCMD (SATA_AHCI_PORTCNTRL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ICC | 31:28 | rwNormal read/write | 0x0 | Interface Communication Control (ICC): Control power management states of the interface. If the Link layer is currently in the L_IDLE state or L_NoCommPower state, writes to this field shall cause the HBA to initiate a transition to the interface power management state requested. If the Link layer is not currently in the L_IDLE state or L_NoCommPower state, writes to this field shall have no effect. When system software writes a non-reserved value other than No-Op (0h), the HBA shall perform the actions described above (for the value written) and update this field back to Idle (0h). If software writes to this field to change the state to a state the link is already in (i.e. interface is in the active state and a request is made to go to the active state), the HBA shall take no action and return this field to Idle. If the interface is in a low power state and software wants to transition to a different low power state, software must first bring the link to active and then initiate the transition to the desired low power state. If CAPS2.DESO is cleared to 0, transition to DevSleep may occur from any other interface state. If CAP2.DESO is set to 1, then DevSleep may only be transitioned to if the interface is in Slumber. 0: Idle 1: Active 2: Partial 6: Slumber 8: DevSleep others: reserved |
| ASP | 27 | rwNormal read/write | 0x0 | Aggressive Slumber / Partial (ASP): When set to 1, and ALPE is set, the HBA shall aggressively enter the Slumber state when it clears the PxCI register and the PxSACT register is cleared or when it clears the PxSACT register and PxCI is cleared. When cleared, and ALPE is set, the HBA shall aggressively enter the Partial state when it clears the PxCI register and the PxSACT register is cleared or when it clears the PxSACT register and PxCI is cleared. If CAP.SALP is cleared to 0 software shall treat this bit as reserved. See section 8.3.1.3 for details. |
| ALPE | 26 | rwNormal read/write | 0x0 | Aggressive Link Power Management Enable (ALPE): When set to 1, the HBA shall aggressively enter a lower link power state (Partial or Slumber) based upon the setting of the ASP bit. Software shall only set this bit to 1 if CAP.SALP is set to 1; if CAP.SALP is cleared to 0 software shall treat this bit as reserved. See section 8.3.1.3 for details. |
| DLAE | 25 | rwNormal read/write | 0x0 | Drive LED on ATAPI Enable (DLAE): When set to 1, the HBA shall drive the LED pin active for commands regardless of the state of PxCMD.ATAPI. When cleared, the HBA shall only drive the LED pin active for commands if PxCMD.ATAPI set to 0. See section 10.11 for details on the activity LED. |
| ATAPI | 24 | rwNormal read/write | 0x0 | Device is ATAPI (ATAPI): When set to 1, the connected device is an ATAPI device. This bit is used by the HBA to control whether or not to generate the desktop LED when commands are active. See section 10.11 for details on the activity LED. |
| APSTE | 23 | rwNormal read/write | 0x0 | Automatic Partial to Slumber Transitions Enabled (APSTE): When set to 1, the HBA may perform Automatic Partial to Slumber Transitions. When cleared to 0 the port shall not perform Automatic Partial to Slumber Transitions. Software shall only set this bit to 1 if CAP2.APST is set to 1; if CAP2.APST is cleared to 0 software shall treat this bit as reserved. |
| FBSCP | 22 | roRead-only | 0x1 | FIS-based Switching Capable Port (FBSCP): When set to 1, indicates that this port supports Port Multiplier FIS-based switching. When cleared to 0, indicates that this port does not support FIS-based switching. This bit may only be set to 1 if both CAP.SPM and CAP.FBSS are set to 1. |
| ESP | 21 | roRead-only | 0x0 | External SATA Port (ESP): When set this bit is set to 1, indicates that this ports signal connector is externally accessible on a signal only connector (e.g. eSATA connector). When set to 1, CAP.SXS shall be set to 1. When cleared to 0, indicates that this ports signal connector is not externally accessible on a signal only connector. ESP is mutually exclusive with the HPCP bit in this register. If ESP is set to 1, then the port may experience hot plug events. |
| CPD | 20 | roRead-only | 0x0 | Cold Presence Detection (CPD): If set to 1, the platform supports cold presence detection on this port. If cleared to 0, the platform does not support cold presence detection on this port. When this bit is set to 1, PxCMD.HPCP should also be set to 1. |
| MPSP | 19 | roRead-only | 0x0 | Mechanical Presence Switch Attached to Port (MPSP): If set to 1, the platform supports an mechanical presence switch attached to this port. If cleared to 0, the platform does not support a mechanical presence switch attached to this port. When this bit is set to 1, PxCMD.HPCP should also be set to 1. |
| HPCP | 18 | roRead-only | 0x0 | Hot Plug Capable Port (HPCP): When set to 1, indicates that this ports signal and power connectors are externally accessible via a joint signal and power connector for blindmate device hot plug. When cleared to 0, indicates that this ports signal and power connectors are not externally accessible via a joint signal and power connector. HPCP is mutually exclusive with the ESP bit in this register. |
| PMA | 17 | rwNormal read/write | 0x0 | Port Multiplier Attached (PMA): This bit is read/write for HBAs that support a Port Multiplier (CAP.SPM = 1). This bit is read-only for HBAs that do not support a port Multiplier (CAP.SPM = 0). When set to 1 by software, a Port Multiplier is attached to the HBA for this port. When cleared to 0 by software, a Port Multiplier is not attached to the HBA for this port. Software is responsible for detecting whether a Port Multiplier is present; hardware does not auto-detect the presence of a Port Multiplier. Software shall only set this bit to 1 when PxCMD.ST is cleared to 0. |
| CPS | 16 | roRead-only | 0x0 | Cold Presence State (CPS): The CPS bit reports whether a device is currently detected on this port via cold presence detection. If CPS is set to 1, then the HBA detects via cold presence that a device is attached to this port. If CPS is cleared to 0 , then the HBA detects via cold presence that there is no device attached to this port. |
| CR | 15 | roRead-only | 0x0 | Command List Running (CR): When this bit is set, the command list DMA engine for the port is running. See the AHCI state machine in section 5.3.2 for details on when this bit is set and cleared by the HBA. |
| FR | 14 | roRead-only | 0x0 | FIS Receive Running (FR): When set, the FIS Receive DMA engine for the port is running. See section 10.3.2 for details on when this bit is set and cleared by the HBA. |
| MPSS | 13 | roRead-only | 0x0 | Mechanical Presence Switch State (MPSS): The MPSS bit reports the state of a mechanical presence switch attached to this port. If CAP.SMPS is set to 1 and the mechanical presence switch is closed then this bit is cleared to 0. If CAP.SMPS is set to 1 and the mechanical presence switch is open then this bit is set to 1. If CAP.SMPS is set to 0 then this bit is cleared to 0. Software should only use this bit if both CAP.SMPS and PxCMD.MPSP are set to 1. |
| CCS | 12:8 | roRead-only | 0x0 | Current Command Slot (CCS): This field is valid when PxCMD.ST is set to 1 and shall be set to the command slot value of the command that is currently being issued by the HBA. When PxCMD.ST transitions from 1 to 0, this field shall be reset to 0. After PxCMD.ST transitions from 0 to 1, the highest priority slot to issue from next is command slot 0. After the first command has been issued, the highest priority slot to issue from next is PxCMD.CCS + 1. For example, after the HBA has issued its first command, if CCS = 0h and PxCI is set to 3h, the next command that will be issued is from command slot 1. |
| Reserved | 7:5 | roRead-only | 0x0 | Reserved |
| FRE | 4 | rwNormal read/write | 0x0 | FIS Receive Enable (FRE): When set, the HBA may post received FISes into the FIS receive area pointed to by PxFB (and for 64-bit HBAs, PxFBU). When cleared, received FISes are not accepted by the HBA, except for the first D2H register FIS after the initialization sequence, and no FISes are posted to the FIS receive area. System software must not set this bit until PxFB (PxFBU) have been programmed with a valid pointer to the FIS receive area, and if software wishes to move the base, this bit must first be cleared, and software must wait for the FR bit in this register to be cleared. Refer to section 10.3.2 for important restrictions on when FRE can be set and cleared. |
| CLO | 3 | rwNormal read/write | 0x0 | Command List Override (CLO): Setting this bit to 1 causes PxTFD.STS.BSY and PxTFD.STS.DRQ to be cleared to 0. This allows a software reset to be transmitted to the device regardless of whether the BSY and DRQ bits are still set in the PxTFD.STS register. The HBA sets this bit to 0 when PxTFD.STS.BSY and PxTFD.STS.DRQ have been cleared to 0. A write to this register with a value of 0 shall have no effect. This bit shall only be set to 1 immediately prior to setting the PxCMD.ST bit to 1 from a previous value of 0. Setting this bit to 1 at any other time is not supported and will result in indeterminate behavior. Software must wait for CLO to be cleared to 0 before setting PxCMD.ST to 1. |
| POD | 2 | roRead-only | 0x0 | Power On Device (POD): This bit is read/write for HBAs that support cold presence detection on this port as indicated by PxCMD.CPD set to 1. This bit is read only 1 for HBAs that do not support cold presence detect. When set, the HBA sets the state of a pin on the HBA to 1 so that it may be used to provide power to a cold-presence detectable port. |
| SUD | 1 | roRead-only | 0x0 | Spin-Up Device (SUD): This bit is read/write for HBAs that support staggered spin-up via CAP.SSS. This bit is read only 1 for HBAs that do not support staggered spin-up. On an edge detect from 0 to 1, the HBA shall start a COMRESET initializatoin sequence to the device. Clearing this bit to 0 does not cause any OOB signal to be sent on the interface. When this bit is cleared to 0 and PxSCTL.DET=0h, the HBA will enter listen mode as detailed in section 10.10.1. |
| ST | 0 | rwNormal read/write | 0x0 | Start (ST): When set, the HBA may process the command list. When cleared, the HBA may not process the command list. Whenever this bit is changed from a 0 to a 1, the HBA starts processing the command list at entry 0. Whenever this bit is changed from a 1 to a 0, the PxCI register is cleared by the HBA upon the HBA putting the controller into an idle state. This bit shall only be set to 1 by software after PxCMD.FRE has been set to 1. Refer to section 10.3.1 for important restrictions on when ST can be set to 1. |