IMOD_2 (USB3_XHCI) Register Description
| Register Name | IMOD_2 |
|---|---|
| Offset Address | 0x00000004A4 |
| Absolute Address |
0x00FE2004A4 (USB3_0_XHCI) 0x00FE3004A4 (USB3_1_XHCI) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000FA0 |
| Description | Interrupter Moderation Register The software may use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC, regardless of USB traffic conditions. To independently validate configuration settings, software may use the following algorithm to convert the inter-interrupt Interval value to the common interrupts/sec performance metric. Instance 2 of an array of 4. |
IMOD_2 (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| IMODC | 31:16 | rwNormal read/write | 0x0 | Interrupt Moderation Counter (IMODC) - RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to 0, counts down to 0, and stops. The associated interrupt is signaled whenever this counter is 0, the Event Ring is not empty, the IE and IP flags = 1, and EHB = 0. This counter may be directly written by software at any time to alter the interrupt rate. |
| IMODI | 15:0 | rwNormal read/write | 0xFA0 | Interrupt Moderation Interval (IMODI) - RW. Default = 4000 (~1ms). Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of 0 disables interrupt throttling logic and interrupts is generated immediately if IP = 0, EHB = 0, and the Event Ring is not empty. |