SMMU_CB10_CONTEXTIDR (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_CB10_CONTEXTIDR (SMMU500) Register Description

Register NameSMMU_CB10_CONTEXTIDR
Offset Address0x000001A034
Absolute Address 0x00FD81A034 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionIdentifies the current process identifier and the current address space identifier

SMMU_CB10_CONTEXTIDR (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PROCID31:8rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ASID 7:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details