WDT_CLK_SEL (IOU_SLCR) Register Description
| Register Name | WDT_CLK_SEL |
|---|---|
| Offset Address | 0x0000000300 |
| Absolute Address | 0x00FF180300 (IOU_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | SWDT clock source select |
WDT_CLK_SEL (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
| SELECT | 0 | rwNormal read/write | 0x0 | System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout via MIO |