enable_periph_id_3 (PL390) Register Description
| Register Name | enable_periph_id_3 |
|---|---|
| Offset Address | 0x0000000FDC |
| Absolute Address | 0x00F9000FDC (RCPU_GIC) |
| Width | 8 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | The periph_id_[8:0] Registers provide information about the configuration of the peripheral. Note some fields span across adjacent registers. |
enable_periph_id_3 (PL390) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| RevAnd | 7:4 | roRead-only | 0x0 | The top-level RTL provides four AND gates that are tied-off to provide an output value of 0x0. Once silicon is available, if metal fixes are necessary then the manufacturer can modify the tie-offs to indicate that a revision of the silicon has occurred. |
| mod_number | 3:0 | roRead-only | 0x0 | The customer can update this field if they modify the RTL of the GIC. Arm set this to 0x0. |