GTXFIFOSIZ0 (USB3_XHCI) Register Description
| Register Name | GTXFIFOSIZ0 |
|---|---|
| Offset Address | 0x000000C300 |
| Absolute Address |
0x00FE20C300 (USB3_0_XHCI) 0x00FE30C300 (USB3_1_XHCI) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000042 |
| Description | Global Transmit FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented TxFIFO. The number of TxFIFOs depends on the configuration parameters including the number of Device IN Endpoints, number of Host Bus Instances, and presence of Debug Capability. The register default values for each mode are assigned based on the maximum packet size, number of packets to be buffered, speed of host bus instance, bus latency, and mode of operation (host, device, or, DBC). Upon reset and mode transitions, hardware automatically programs these registers to the default values. Consequently, there is typically no need for the software to modify the pre-defined default values. For the debug capability mode, the currently mapped EP0 IN and EP1 IN TxFIFO numbers can be read from the GFIFOPRIDBC register. For OTG mode of operation, when the core is transitioning to host mode, program GTXFIFOSIZ register to the correct value only after OCTL.PeriMode is programmed to 1b0. |
GTXFIFOSIZ0 (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TXFSTADDR_N | 31:16 | rwNormal read/write | 0x0 | Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words. |
| TXFDEP_N | 15:0 | rwNormal read/write | 0x42 | TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32,768 |