ERR_ATB_IMR (LPD_SLCR) Register Description
| Register Name | ERR_ATB_IMR |
|---|---|
| Offset Address | 0x0000006004 |
| Absolute Address | 0x00FF416004 (LPD_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000003 |
| Description | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
ERR_ATB_IMR (LPD_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | razRead as zero | 0x0 | reserved for future use |
| afifs2 | 1 | roRead-only | 0x1 | ISR for ATB placed between lpd interconnect and afifs2 |
| lpdm | 0 | roRead-only | 0x1 | IMR for ATB placed between lpd inbound switch and lpd main switch (trans. going to Slave in LPD including IOU) |