counter_control_register (IOU_SCNTRS) Register Description
| Register Name | counter_control_register |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address | 0x00FF260000 (IOU_SCNTRS) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Controls the counter increments. This register is not accessible to the read-only programming interface. |
counter_control_register (IOU_SCNTRS) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | razRead as zero | 0x0 | Not Used |
| HDBG | 1 | rwNormal read/write | 0x0 | Halt on Debug 0: Do not halt on debug, HLTDBG signal into the counter has no effect. 1: Halt on debug, when HLTDBG is driven HIGH, the count value is held static. |
| EN | 0 | rwNormal read/write | 0x0 | Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing. |