zero (RSA_CORE) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

zero (RSA_CORE) Register Description

Register Namezero
Offset Address0x0000000028
Absolute Address 0x00FFCE0028 (RSA_CORE)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionRSA Zero

zero (RSA_CORE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
zero 0woWrite-only0x0Writing 1 zeroes the write buffer (this bit is self-clearing). Can be used to avoid writing the zero-value LSB bytes of the word. For example, to write one or more all-zero words, the CPU shall write a 1 to this register, then commit the write buffer to the memory addresses through one or more write to the RSA_WR_ADDR register. To write the word with zero LSB bytes, the CPU shall write a 1 to this register, then write the non-zero MSB bytes to the RSA_WR_DATA register (starting with the least significant one), then commit the buffer by writing the memory address to the RSA_WR_ADDR register.