Tx_FIFO_trigger_level (UART) Register Description
| Register Name | Tx_FIFO_trigger_level |
|---|---|
| Offset Address | 0x0000000044 |
| Absolute Address |
0x00FF000044 (UART0) 0x00FF010044 (UART1) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000020 |
| Description | Transmitter FIFO Trigger Level Register |
The read/write Transmitter FIFO Trigger Level Register is used to set the value at which the transmitter FIFO triggers an interrupt event.
Tx_FIFO_trigger_level (UART) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:6 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| TTRIG | 5:0 | rwNormal read/write | 0x20 | Transmitter FIFO trigger level: 0: Disables transmitter FIFO trigger level function 1 - 63: Trigger set when transmitter FIFO fills to TTRIG bytes |