OCM_PWR_STATUS (PMU_LOCAL) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

OCM_PWR_STATUS (PMU_LOCAL) Register Description

Register NameOCM_PWR_STATUS
Offset Address0x00000000CC
Absolute Address 0x00FFD600CC (PMU_LOCAL)
Width32
TyperoRead-only
Reset Value0x01010101
DescriptionOCM Memory Power Status.

Status of the power switch gates. 0: off. 1: on, ready. All fields are read-only and are accessible only by the PMU processor.

OCM_PWR_STATUS (PMU_LOCAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0reserved
Bank324roRead-only0x1OCM Bank 3
Reserved23:17roRead-only0x0reserved
Bank216roRead-only0x1OCM Bank 2
Reserved15:9roRead-only0x0reserved
Bank1 8roRead-only0x1OCM Bank 1
Reserved 7:1roRead-only0x0reserved
Bank0 0roRead-only0x1OCM Bank 0