APM1_CFG (VCU_SLCR) Register Description
| Register Name | APM1_CFG |
|---|---|
| Offset Address | 0x0000000200 |
| Absolute Address | 0x00A0040200 (VCU_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000002 |
| Description | APM1_CFG |
APM1_CFG (VCU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| rd_id_lat_ff1 | 31:28 | rwNormal read/write | 0x0 | read ID considered for latency calculation in 2nd read FIFO |
| wr_id_lat_ff1 | 27:24 | rwNormal read/write | 0x0 | write ID considered for latency calculation in 2nd write FIFO |
| rd_id_lat_ff0 | 23:20 | rwNormal read/write | 0x0 | read ID considered for latency calculation in 1st read FIFO |
| wr_id_lat_ff0 | 19:16 | rwNormal read/write | 0x0 | write ID considered for latency calculation in 1st write FIFO |
| Reserved | 15:8 | razRead as zero | 0x0 | reserved |
| sel_rd_id_lat_ff1 | 7 | rwNormal read/write | 0x0 | 0: rd_lat_id considered for latency calculation 1: All IDs considered for latency calculation |
| sel_wr_id_lat_ff1 | 6 | rwNormal read/write | 0x0 | 0: wr_lat_id considered for latency calculation 1: All IDs considered for latency calculation |
| sel_rd_id_lat_ff0 | 5 | rwNormal read/write | 0x0 | 0: rd_lat_id considered for latency calculation 1: All IDs considered for latency calculation |
| sel_wr_id_lat_ff0 | 4 | rwNormal read/write | 0x0 | 0: wr_lat_id considered for latency calculation 1: All IDs considered for latency calculation |
| Reserved | 3 | razRead as zero | 0x0 | reserved |
| mode | 2 | rwNormal read/write | 0x0 | 0: Contineous Timing Mode. Mode 1 in the APM specification 1: Burst Timing Mode. Mode 2 in the APM specification |
| enable | 1 | rwNormal read/write | 0x1 | 0: APM disabled 1: APM Enabled |
| Reserved | 0 | razRead as zero | 0x0 | reserved |