DRAMTMG9_SHADOW (DDRC) Register Description
Register Name | DRAMTMG9_SHADOW |
---|---|
Offset Address | 0x0000002124 |
Absolute Address | 0x00FD072124 (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x0004040D |
Description | SDRAM Timing Shadow Register 9 |
All register fields are quasi-dynamic group 2 and group 4, unless described otherwise in the register field description. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
DRAMTMG9_SHADOW (DDRC) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ddr4_wr_preamble | 30 | rwNormal read/write | 0x0 | DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble |
t_ccd_s | 18:16 | rwNormal read/write | 0x4 | DDR4: tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank a to bank b), the minimum time is this value + 1. Program this to (tCCD_S/2) and round it up to the next integer value. Unit: clocks. |
t_rrd_s | 11:8 | rwNormal read/write | 0x4 | DDR4: tRRD_S: Minimum time between activates from bank a to bank b for different bank group. Program this to (tRRD_S/2) and round it up to the next integer value. Unit: Clocks. |
wr2rd_s | 5:0 | rwNormal read/write | 0xD | DDR4: CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. This comes directly from the SDRAM specification. Divide the value calculated using the above equation by 2, and round it up to next integer. Programming Mode: Quasi-dynamic Group 1, Group 2, and Group 4 |