IMR (XPPU) Register Description
| Register Name | IMR |
|---|
| Offset Address | 0x0000000014 |
|---|
| Absolute Address |
0x00FF980014 (LPD_XPPU)
|
|---|
| Width | 32 |
|---|
| Type | roRead-only |
|---|
| Reset Value | 0x000000EF |
|---|
| Description | Interrupt Mask. |
|---|
0: enabled. 1: masked (disabled). If the ISR bit = 1 (asserted interrupt) and the IMR bit = 0 (not masked), then the IRQ to the interrupt controller is asserted. Software checks the ISR to determine the cause of the interrupt. Read-only.
IMR (XPPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:8 | roRead-only | 0x0 | reserved |
| APER_PARITY | 7 | roRead-only | 0x1 | Parity Error Detected. |
| APER_TZ | 6 | roRead-only | 0x1 | TrustZone Violation. |
| APER_PERM | 5 | roRead-only | 0x1 | Master ID Access Violation. |
| Reserved | 4 | roRead-only | 0x0 | reserved |
| MID_PARITY | 3 | roRead-only | 0x1 | Master ID Parity Error. |
| MID_RO | 2 | roRead-only | 0x1 | Read permission Violation. |
| MID_MISS | 1 | roRead-only | 0x1 | Master ID Not Found. |
| INV_APB | 0 | roRead-only | 0x1 | Register Access Error on APB. |