QSPIDMA_DST_ADDR (QSPI) Register Description
| Register Name | QSPIDMA_DST_ADDR |
|---|---|
| Offset Address | 0x0000000800 |
| Absolute Address | 0x00FF0F0800 (QSPI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DMA destination memory address |
For DMA stream-to-memory data transfer.
QSPIDMA_DST_ADDR (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ADDR | 31:2 | woWrite-only | 0x0 | Destination memory address for DMA stream to memory data transfer Address is word aligned, so this field is only 30-bits. (2 lsbs are 0) This field must be written initially before a DMA operation is started. In this case, it indicates the memory destination address the DMA will begin writing to. Note: Change this value only when controller is not communicating with the memory device. |
| Reserved | 1:0 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |