rpuM1_intlpd_max_ot (LPD_GPV) Register Description
| Register Name | rpuM1_intlpd_max_ot |
|---|---|
| Offset Address | 0x0000043110 |
| Absolute Address | 0x00FE143110 (LPD_GPV) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Maximum number of outstanding transactions |
A value of 0 for both the integer and fractional parts disables the programmable regulation so that the NIC-301 base product configuration limits apply. A value of 0 for the fractional part programs disables the regulation of fractional outstanding transactions. The AW and AR outstanding transaction limits are enabled when you set the corresponding en_aw_ot or en_ar_ot control bits of the QoS control register.
rpuM1_intlpd_max_ot (LPD_GPV) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ar_max_oti | 29:24 | rwNormal read/write | 0x0 | Integer part of max outstanding AR addresses. |
| ar_max_otf | 23:16 | rwNormal read/write | 0x0 | Fraction part of max outstanding AR addresses. |
| aw_max_oti | 13:8 | rwNormal read/write | 0x0 | Integer part of max outstanding AW addresses. |
| aw_max_otf | 7:0 | rwNormal read/write | 0x0 | Fraction part of max outstanding AW addresses. |
The maximum number of outstanding transactions register enables you to program the maximum number of address requests for the AR and AW channels. The outstanding transaction limits have an integer part and a fractional part.