PP1_WB2_MRT_ENABLE (GPU) Register Description
| Register Name | PP1_WB2_MRT_ENABLE |
|---|---|
| Offset Address | 0x000000A31C |
| Absolute Address | 0x00FD4BA31C (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | WB2 MRT Enable Register |
PP1_WB2_MRT_ENABLE (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
| WB2_MRT_ENABLE | 3:0 | rwNormal read/write | 0x0 | 0 MRT 0 enabled 1 MRT 1 enabled 2 MRT 2 enabled 3 MRT 3 enabled |