L0_TM_DIG_8 (SERDES) Register Description
| Register Name | L0_TM_DIG_8 |
|---|---|
| Offset Address | 0x0000001074 |
| Absolute Address | 0x00FD401074 (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L0_TM_DIG_8 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TM_DIG_8_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| Reserved | 7:5 | roRead-only | 0x0 | Value generated by PCW. |
| eyesurf_enable | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| use_EB_in_MPHY | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
| bypass_EB | 2 | rwNormal read/write | 0x0 | Value generated by PCW. |
| EB_mode | 1 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_EB_mode | 0 | rwNormal read/write | 0x0 | Value generated by PCW. |