bank1_ctrl5 (IOU_SLCR) Register Description
| Register Name | bank1_ctrl5 |
|---|---|
| Offset Address | 0x0000000164 |
| Absolute Address | 0x00FF180164 (IOU_SLCR) |
| Width | 26 |
| Type | rwNormal read/write |
| Reset Value | 0x03FFFFFF |
| Description | MIO Bank 1, Pull up/down enable. |
bank1_ctrl5 (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| pull_enable | 25:0 | rwNormal read/write | 0x3FFFFFF | Enable the internal pull-up or pull-down resistors on MIO pins [26:51]. 0 = disable. 1 = enable. Select between a pull-up and pull-down using the bank1_ctrl4 register. Bit [0] controls MIO pin 38. Bit [1] controls MIO pin 39. Bit [2] controls MIO pin 40. Bit [3] controls MIO pin 41. Bit [4] controls MIO pin 42. Bit [5] controls MIO pin 43. Bit [6] controls MIO pin 44. Bit [7] controls MIO pin 45. Bit [8] controls MIO pin 46. Bit [9] controls MIO pin 47. Bit [10] controls MIO pin 48. Bit [11] controls MIO pin 49. Bit [12] controls MIO pin 50. Bit [13] controls MIO pin 51. Bit [14] controls MIO pin 26. Bit [15] controls MIO pin 27. Bit [16] controls MIO pin 28. Bit [17] controls MIO pin 29. Bit [18] controls MIO pin 30. Bit [19] controls MIO pin 31. Bit [20] controls MIO pin 32. Bit [21] controls MIO pin 33. Bit [22] controls MIO pin 34. Bit [23] controls MIO pin 35. Bit [24] controls MIO pin 36. Bit [25] controls MIO pin 37. Bits [26] to [31] are reserved. |