reg_softwarereset (SDIO) Register Description
| Register Name | reg_softwarereset |
|---|---|
| Offset Address | 0x000000002F |
| Absolute Address |
0x00FF16002F (SD0) 0x00FF17002F (SD1) |
| Width | 8 |
| Type | clronwrReadable, clears value on write |
| Reset Value | 0x00000000 |
| Description | Software reset for data, command and all. |
reg_softwarereset (SDIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| swreset_for_dat | 2 | clronwrReadable, clears value on write | 0x0 | Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register: Buffer is cleared and Initialized. Present State register: Buffer read Enable, Buffer write Enable, Read Transfer Active, Write Transfer Active, DAT Line Active, Command Inhibit (DAT). Block Gap Control register: Continue Request, Stop At Block Gap Request. Normal Interrupt Status register: Buffer Read Ready, Buffer Write Ready, Block Gap Event, Transfer Complete. 0: Operational. 1: Held in reset. |
| swreset_for_cmd | 1 | clronwrReadable, clears value on write | 0x0 | Only part of command circuit is reset. The following registers and bits are cleared by this bit: Present State register- Command Inhibit (CMD). Normal Interrupt Status register- Command Complete. 0: Operational. 1: Held in reset. |
| swreset_for_all | 0 | clronwrReadable, clears value on write | 0x0 | This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when capabilities registers are valid and the HD can read them. Additional use of Software Reset For All may not affect the value of the Capabilities registers. If this bit is set to 1, the SD card shall reset itself and must be re initialized by the HD. 0: Operational. 1: Held in reset. |