Field Name | Bits | Type | Reset Value | Description |
NOS7 | 31 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
NOS6 | 30 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
NOS5 | 29 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
NOS4 | 28 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
NOS3 | 27 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
NOS2 | 26 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
NOS1 | 25 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
NOS0 | 24 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
NS1 | 19 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
NS0 | 18 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
DS1 | 17 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
DS0 | 16 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TR7 | 15:14 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TR6 | 13:12 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TR5 | 11:10 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TR4 | 9:8 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TR3 | 7:6 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TR2 | 5:4 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TR1 | 3:2 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TR0 | 1:0 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |