GP_CONTR_REG_PLBCL_END_ADDR (GPU) Register Description
| Register Name | GP_CONTR_REG_PLBCL_END_ADDR |
|---|---|
| Offset Address | 0x000000000C |
| Absolute Address | 0x00FD4B000C (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | GP Control Register PLBCL End Address |
GP_CONTR_REG_PLBCL_END_ADDR (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| GP_CONTR_REG_PLBCL_END_ADDR | 31:3 | rwNormal read/write | 0x0 | End address of PLB command list |
| Reserved | 2:0 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined |