DX3MDLR1 (DDR_PHY) Register Description
| Register Name | DX3MDLR1 |
|---|---|
| Offset Address | 0x0000000AA4 |
| Absolute Address | 0x00FD080AA4 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DATX8 n Master Delay Line Register 1 |
DX3MDLR1 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:9 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| MDLD | 8:0 | rwNormal read/write | 0x0 | MDL Delay: Delay select for the LCDL for the Master Delay Line. |