MIO_MST_TRI1 (IOU_SLCR) Register

MIO_MST_TRI1 (IOU_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2025-06-20

Revision

1.11

MIO_MST_TRI1 (IOU_SLCR) Register Description

Register Name	MIO_MST_TRI1
Offset Address	0x0000000208
Absolute Address	0x00FF180208 (IOU_SLCR)
Width	32
Type	rwNormal read/write
Reset Value	0xFFFFFFFF
Description	MIO pin Tri-state Enables, 63:32

Parallel access to the master tri-state enables for MIO pins

MIO_MST_TRI1 (IOU_SLCR) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
PIN_63_TRI	31	rwNormal read/write	0x1	Master Tri-state Enable for pin 63, active high
PIN_62_TRI	30	rwNormal read/write	0x1	Master Tri-state Enable for pin 62, active high
PIN_61_TRI	29	rwNormal read/write	0x1	Master Tri-state Enable for pin 61, active high
PIN_60_TRI	28	rwNormal read/write	0x1	Master Tri-state Enable for pin 60, active high
PIN_59_TRI	27	rwNormal read/write	0x1	Master Tri-state Enable for pin 59, active high
PIN_58_TRI	26	rwNormal read/write	0x1	Master Tri-state Enable for pin 58, active high
PIN_57_TRI	25	rwNormal read/write	0x1	Master Tri-state Enable for pin 57, active high
PIN_56_TRI	24	rwNormal read/write	0x1	Master Tri-state Enable for pin 56, active high
PIN_55_TRI	23	rwNormal read/write	0x1	Master Tri-state Enable for pin 55, active high
PIN_54_TRI	22	rwNormal read/write	0x1	Master Tri-state Enable for pin 54, active high
PIN_53_TRI	21	rwNormal read/write	0x1	Master Tri-state Enable for pin 53, active high
PIN_52_TRI	20	rwNormal read/write	0x1	Master Tri-state Enable for pin 52, active high
PIN_51_TRI	19	rwNormal read/write	0x1	Master Tri-state Enable for pin 51, active high
PIN_50_TRI	18	rwNormal read/write	0x1	Master Tri-state Enable for pin 50, active high
PIN_49_TRI	17	rwNormal read/write	0x1	Master Tri-state Enable for pin 49, active high
PIN_48_TRI	16	rwNormal read/write	0x1	Master Tri-state Enable for pin 48, active high
PIN_47_TRI	15	rwNormal read/write	0x1	Master Tri-state Enable for pin 47, active high
PIN_46_TRI	14	rwNormal read/write	0x1	Master Tri-state Enable for pin 46, active high
PIN_45_TRI	13	rwNormal read/write	0x1	Master Tri-state Enable for pin 45, active high
PIN_44_TRI	12	rwNormal read/write	0x1	Master Tri-state Enable for pin 44, active high
PIN_43_TRI	11	rwNormal read/write	0x1	Master Tri-state Enable for pin 43, active high
PIN_42_TRI	10	rwNormal read/write	0x1	Master Tri-state Enable for pin 42, active high
PIN_41_TRI	9	rwNormal read/write	0x1	Master Tri-state Enable for pin 41, active high
PIN_40_TRI	8	rwNormal read/write	0x1	Master Tri-state Enable for pin 40, active high
PIN_39_TRI	7	rwNormal read/write	0x1	Master Tri-state Enable for pin 39, active high
PIN_38_TRI	6	rwNormal read/write	0x1	Master Tri-state Enable for pin 38, active high
PIN_37_TRI	5	rwNormal read/write	0x1	Master Tri-state Enable for pin 37, active high
PIN_36_TRI	4	rwNormal read/write	0x1	Master Tri-state Enable for pin 36, active high
PIN_35_TRI	3	rwNormal read/write	0x1	Master Tri-state Enable for pin 35, active high
PIN_34_TRI	2	rwNormal read/write	0x1	Master Tri-state Enable for pin 34, active high
PIN_33_TRI	1	rwNormal read/write	0x1	Master Tri-state Enable for pin 33, active high
PIN_32_TRI	0	rwNormal read/write	0x1	Master Tri-state Enable for pin 32, active high