PP1_ABGR_CLEAR_VALUE_2 (GPU) Register Description
| Register Name | PP1_ABGR_CLEAR_VALUE_2 |
|---|---|
| Offset Address | 0x000000A020 |
| Absolute Address | 0x00FD4BA020 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | ABGR Clear Value 2 Register |
PP1_ABGR_CLEAR_VALUE_2 (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ALPHA_CLEAR_VALUE | 31:24 | rwNormal read/write | 0x0 | Alpha clear value when FP_TILEBUF_ENABLE==0 , [31:0] Reserved, write as zero, read undefined when FP_TILEBUF_ENABLE==1 |
| BLUE_CLEAR_VALUE | 23:16 | rwNormal read/write | 0x0 | Blue clear value when FP_TILEBUF_ENABLE==0 |
| GREEN_CLEAR_VALUE | 15:8 | rwNormal read/write | 0x0 | Green clear value when FP_TILEBUF_ENABLE==0 |
| RED_CLEAR_VALUE | 7:0 | rwNormal read/write | 0x0 | Red clear value when FP_TILEBUF_ENABLE==0 |