SMMU_NSGFSRRESTORE (SMMU500) Register - SMMU_NSGFSRRESTORE (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

SMMU_NSGFSRRESTORE (SMMU500) Register Description

Register NameSMMU_NSGFSRRESTORE
Offset Address0x000000044C
Absolute Address 0x00FD80044C (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionRestores the state of SMMU_GFSR, after a reset, for example.

SMMU_NSGFSRRESTORE (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MULTI31woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
UUT 8woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
EF 6woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CAF 5woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
UCIF 4woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
UCBF 3woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SMCF 2woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
USF 1woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ICF 0woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details