MIO_PIN_61 (IOU_SLCR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MIO_PIN_61 (IOU_SLCR) Register Description

Register NameMIO_PIN_61
Offset Address0x00000000F4
Absolute Address 0x00FF1800F4 (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Device Pin 61 Multiplexer Controls.

MIO_PIN_61 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [61] input/output bank 2.)
1: CAN1 RX input.
2: I2C1 SDA input/output.
3: PJTAG TMS input.
4: SPI1 SS [0] input/output.
5: TTC1 waveform output.
6: UART1 RxD input.
7: TracePort DQ[7] output.
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: reserved
2: reserved
3: reserved
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: USB0 ULPI Data [5] input/output.
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: GEM2 RGMII Rx Data [2] input.
Reserved 0rwNormal read/write0x0reserved