PP1_FS_STACK_ADDR (GPU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PP1_FS_STACK_ADDR (GPU) Register Description

Register NamePP1_FS_STACK_ADDR
Offset Address0x000000A030
Absolute Address 0x00FD4BA030 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionFS Stack Address Register

PP1_FS_STACK_ADDR (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
FS_STACK_ADDR31:6rwNormal read/write0x0Fragment shader stack address
_ 5:0rwNormal read/write0x0Reserved, write as zero, read undefined.