INT_FPD (FPD_SLCR) Register Description
| Register Name | INT_FPD |
|---|---|
| Offset Address | 0x0000000200 |
| Absolute Address | 0x00FD610200 (FPD_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interconnect Clock Source Select |
INT_FPD (FPD_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | Reserved for future use |
| gfm_sel | 0 | rwNormal read/write | 0x0 | Clock Source select for FPD Interconnect components that interface to LPD. This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. 0: Default. Use LPD Clocks. This setting must be used when LPD and FPD need to commmunicate 1: Use clock originating in FPD. This option must be used when LPD and FPD are isolated. |