bank0_ctrl0 (IOU_SLCR) Register Description
| Register Name | bank0_ctrl0 |
|---|---|
| Offset Address | 0x0000000138 |
| Absolute Address | 0x00FF180138 (IOU_SLCR) |
| Width | 26 |
| Type | rwNormal read/write |
| Reset Value | 0x03FFFFFF |
| Description | MIO Bank 0, Drive 0 control. |
bank0_ctrl0 (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| drive0 | 25:0 | rwNormal read/write | 0x3FFFFFF | Together with the bank0_ctrl1 [drive1] bit field, controls the output drive strength of MIO pins [0:25]. Drive0 corresponds to MSB and drive1 corresponds to LSB Drive table for [drive0], [drive1]: 00 = 2 mA 01 = 4 mA 10 = 8 mA 11 = 12 mA Bit [0] controls MIO pin 0. .. Bit [25] controls MIO pin 25. Bits [26] to [31] are reserved. Eg: setting bank0_ctrl0 [drive0][bit4] = 0 and bank0_ctrl1 [drive1] [bit4]=1 makes MIO[4] drive strength to 4mA |