GTXFIFOPRIDEV (USB3_XHCI) Register Description
| Register Name | GTXFIFOPRIDEV |
|---|---|
| Offset Address | 0x000000C610 |
| Absolute Address |
0x00FE20C610 (USB3_0_XHCI) 0x00FE30C610 (USB3_1_XHCI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Global Device TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Device TXFIFOs (one per IN endpoint). Each register bit[n] controls the priority (1: high, 0: low) of each TXFIFO[n]. When multiple TXFIFOs compete for DMA service at a given time (that is, multiple TXQs contain TX DMA requests and their corresponding TXFIFOs have space available), the TX DMA arbiter grants access on a packet-basis in the following manner: - 1. High-priority TXFIFOs are granted access using round-robin arbitration - 2. Low-priority TXFIFOs are granted access using round-robin arbitration only after the high-priority TXFIFOs have no further processing to do (that is, either the TXQs are empty or the corresponding TXFIFOs are full). For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed. When configuring periodic IN endpoints, software must set register bit[n]=1, where n is the TXFIFO assignment. This ensures that the DMA for isochronous or interrupt IN endpoints are prioritized over bulk or control IN endpoints. This register is present only when the core is configured to operate in the device mode (includes DRD and OTG modes). The register size corresponds to the number of Device IN endpoints. Note - Since the device mode uses only one RXFIFO, there is no Device RXFIFO DMA Priority Register. |
GTXFIFOPRIDEV (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:6 | roRead-only | 0x0 | Reserved |
| gtxfifopridev | 5:0 | rwNormal read/write | 0 | Device TxFIFO priority |