qspiM_intiou_ib_ar_p (IOU_GPV) Register Description
| Register Name | qspiM_intiou_ib_ar_p |
|---|---|
| Offset Address | 0x000004A124 |
| Absolute Address | 0x00FE04A124 (IOU_GPV) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | AR channel peak rate |
qspiM_intiou_ib_ar_p (IOU_GPV) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ar_p | 31:24 | rwNormal read/write | 0x0 | channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc. |