reg_hostcontrol2 (SDIO) Register Description
| Register Name | reg_hostcontrol2 |
|---|---|
| Offset Address | 0x000000003E |
| Absolute Address |
0x00FF16003E (SD0) 0x00FF17003E (SD1) |
| Width | 16 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | UHS Mode, I/O Drive, Tuning, Clocking, Intr, and Presets. |
Program UHS Select Mode, Driver Strength Select, Execute Tuning, Sampling Clock Select, Asynchronous Interrupt Enable, and Preset value enable.
reg_hostcontrol2 (SDIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| hostctrl2_presetvalueenable | 15 | rwNormal read/write | 0x0 | Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When Preset Value Enable is set to automatic. This bit enables the functions defined in the Preset Value registers. 0 SDCLK and Driver Strength are controlled by Host Driver. 1 Automatic Selection by Preset Value are Enabled. If this bit is set to 0, SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select in Host Control 2 register are set by Host Driver. If this bit is set to 1, SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select in Host Control 2 register are set by Host Controller as specified in the Preset Value registers. |
| hostctrl2_asynchintrenable | 14 | rwNormal read/write | 0x0 | This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver Card Interrupt to the host when it is asserted by the Card. 0 Disabled 1 Enabled |
| hostctrl2_samplingclkselect | 7 | rwNormal read/write | 0x0 | This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is cleared by writing 0. Change of this bit is not allowed while the Host Controller is receiving response or a read data block. 0 Fixed clock is used to sample data 1 Tuned clock is used to sample data |
| hostctrl2_executetuning | 6 | clronwrReadable, clears value on write | 0x0 | This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning procedure. 0 Not Tuned or Tuning Completed 1 Execute Tuning |
| hostctrl2_1p8vsignallingena | 3 | rwNormal read/write | 0x0 | This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails. Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V. 3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling (One of support bits is set to 1: SDR50, SDR104 or DDR50 in the Capabilities register) and the card or device supports UHS-I. 0 3.3V Signalling, 1 1.8V Signalling |
| hostctrl2_uhsmodeselect | 2:0 | rwNormal read/write | 0x0 | This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1.If Preset Value Enable in the Host Control 2 register is set to 1, Host Controller sets SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select according to Preset Value registers. In this case, one of preset value registers is selected by this field. Host Driver needs to reset SD Clock Enable before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets SD Clock Enable again. 000: SDR12 001: SDR25 010: SDR50 011: SDR104 100: DDR50 101 - 111: Reserved. When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more detail. |