RESET_REASON (CRL_APB) Register Description
| Register Name | RESET_REASON |
|---|---|
| Offset Address | 0x0000000220 |
| Absolute Address | 0x00FF5E0220 (CRL_APB) |
| Width | 16 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000001 |
| Description | Records the Reason for the Reset. |
The register is reset only by a POR reset.
RESET_REASON (CRL_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 14:7 | roRead-only | 0x0 | reserved |
| debug_sys | 6 | wtcReadable, write a 1 to clear | 0x0 | Software Debugger Reset. Write to BLOCKONLY_RST [debug_only]. |
| soft | 5 | wtcReadable, write a 1 to clear | 0x0 | Software System Reset. Write to RESET_CTRL [soft_reset]. |
| srst | 4 | wtcReadable, write a 1 to clear | 0x0 | External System Reset; the PS_SRST_B reset signal pin was asserted. |
| psonly_reset_req | 3 | wtcReadable, write a 1 to clear | 0x0 | PS-only Reset. Write to the PMU_GLOBAL.GLOBAL_RESET [PS_ONLY_RST]. Note: After executing the PS-only reboot sequence FSBL clears this bit |
| pmu_sys_reset | 2 | wtcReadable, write a 1 to clear | 0x0 | Internal System Reset. A system error triggered a system reset. |
| internal_por | 1 | wtcReadable, write a 1 to clear | 0x0 | Internal POR. A system error triggered a POR reset. |
| external_por | 0 | wtcReadable, write a 1 to clear | 0x1 | External POR; the PS_POR_B reset signal pin was asserted. |