SMMU_CBFRSYNRA7 (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_CBFRSYNRA7 (SMMU500) Register Description

Register NameSMMU_CBFRSYNRA7
Offset Address0x000000141C
Absolute Address 0x00FD80141C (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionGives fault syndrome information about the access that caused an exception in the associated translation context bank.

SMMU_CBFRSYNRA7 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SSD_Index30:16roRead-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
StreamID14:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details