LOC_AUX_PWR_STATE (PMU_LOCAL) Register Description
| Register Name | LOC_AUX_PWR_STATE |
|---|
| Offset Address | 0x0000000104 |
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| Absolute Address |
0x00FFD60104 (PMU_LOCAL)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x000FF080 |
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| Description | RAM Retention and Processor Emulation States. |
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RAM retention state for the PS memories (1=Retention) and Power-down Emulation State for the Arm processor (1=Powered-down Emulation State). The register maintains its contents during a System Reset.
LOC_AUX_PWR_STATE (PMU_LOCAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| ACPU3_Emul | 31 | rwNormal read/write | 0x0 | APU core 3 power emulation state. |
| ACPU2_Emul | 30 | rwNormal read/write | 0x0 | APU core 2 power emulation state. |
| ACPU1_Emul | 29 | rwNormal read/write | 0x0 | APU core 1 power emulation state. |
| ACPU0_Emul | 28 | rwNormal read/write | 0x0 | APU core 0 power emulation state. |
| RPU_Emul | 27 | rwNormal read/write | 0x0 | RPU MPCore power emulation state. |
| Reserved | 26:20 | roRead-only | 0x0 | reserved |
| OCM_Bank3 | 19 | rwNormal read/write | 0x1 | OCM bank 3 data retension state. |
| OCM_Bank2 | 18 | rwNormal read/write | 0x1 | OCM bank 2 data retension state. |
| OCM_Bank1 | 17 | rwNormal read/write | 0x1 | OCM bank 1 data retension state. |
| OCM_Bank0 | 16 | rwNormal read/write | 0x1 | OCM bank 0 data retension state. |
| TCM1B | 15 | rwNormal read/write | 0x1 | RPU core 1, TCM_B data retension state. |
| TCM1A | 14 | rwNormal read/write | 0x1 | RPU core 1, TCM_A data retension state. |
| TCM0B | 13 | rwNormal read/write | 0x1 | RPU core 0, TCM_B data retension state. |
| TCM0A | 12 | rwNormal read/write | 0x1 | RPU core 0, TCM_A data retension state. |
| Reserved | 11:9 | roRead-only | 0x0 | reserved |
| Reserved | 8 | roRead-only | 0x0 | reserved |
| L2 | 7 | rwNormal read/write | 0x1 | APU L2 Cache data retention state. |
| Reserved | 6:0 | rwNormal read/write | 0x0 | reserved |