IRQ_STATUS (PMU_IOMODULE) Register Description
| Register Name | IRQ_STATUS |
|---|
| Offset Address | 0x0000000030 |
|---|
| Absolute Address |
0x00FFD40030 (PMU_IOMODULE)
|
|---|
| Width | 32 |
|---|
| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Interrupt Status Register |
|---|
The Interrupt Status Register holds information on interrupt events that have occurred. The register is read-only and the IRQ_ACK register should be used to clear individual interrupts
IRQ_STATUS (PMU_IOMODULE) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| CSU_PMU_SEC_LOCK | 31 | roRead-only | 0x0 | Secure lockdown request from CSU |
| Reserved | 30 | razRead as zero | 0x0 | reserved |
| INV_ADDR | 29 | roRead-only | 0x0 | Interrupt for Address Errors generated during accesses to PS SLCRs or PMU Global registers |
| PWR_DN_REQ | 28 | roRead-only | 0x0 | Interrupt to signal a power-down request |
| PWR_UP_REQ | 27 | roRead-only | 0x0 | Interrupt to signal a power-up request |
| SW_RST_REQ | 26 | roRead-only | 0x0 | Interrupt to signal a software-generated reset request |
| HW_RST_REQ | 25 | roRead-only | 0x0 | Interrupt for all hardware-generated Block Reset requests |
| ISO_REQ | 24 | roRead-only | 0x0 | Interrupt to signal an isolation request |
| FW_REQ | 23 | roRead-only | 0x0 | Interrupt to signal a custom request to FW |
| IPI3 | 22 | roRead-only | 0x0 | Interrupt Associated with IPI slice 3 to PMU |
| IPI2 | 21 | roRead-only | 0x0 | Interrupt Associated with IPI slice 2 to PMU |
| IPI1 | 20 | roRead-only | 0x0 | Interrupt Associated with IPI slice 1 to PMU |
| IPI0 | 19 | roRead-only | 0x0 | Interrupt Associated with IPI slice 0 to PMU |
| RTC_ALARM | 18 | roRead-only | 0x0 | Interrupt from RTC to signal the Alarm |
| RTC_EVERY_SECOND | 17 | roRead-only | 0x0 | Interrupt from RTC triggered every second |
| CORRECTABLE_ECC | 16 | roRead-only | 0x0 | Interrupt for a single bit ECC detection in the PMU RAM |
| Reserved | 15 | razRead as zero | 0x0 | reserved |
| GPI3 | 14 | roRead-only | 0x0 | GPI3 changed |
| GPI2 | 13 | roRead-only | 0x0 | GPI2 changed |
| GPI1 | 12 | roRead-only | 0x0 | GPI1 changed |
| GPI0 | 11 | roRead-only | 0x0 | GPI0 changed |
| Reserved | 10:7 | razRead as zero | 0x0 | reserved |
| PIT3 | 6 | roRead-only | 0x0 | PIT3 lapsed |
| PIT2 | 5 | roRead-only | 0x0 | PIT2 lapsed |
| PIT1 | 4 | roRead-only | 0x0 | PIT1 lapsed |
| PIT0 | 3 | roRead-only | 0x0 | PIT0 lapsed |
| Reserved | 2 | razRead as zero | 0x0 | reserved |
| Reserved | 1 | razRead as zero | 0x0 | reserved |
| Reserved | 0 | razRead as zero | 0x0 | reserved |